Channel estimation based on noise power

ABSTRACT

Disclosed are various embodiments providing processor configured to determine a received signal strength indication (RSSI) value for each of the plurality of channel taps. The processing circuitry identifies a maximum RSSI value among the RSSI values and may adjust a variable threshold range according to the maximum RSSI value. The RSSI value for each channel tap may be scaled according to a corresponding per tap noise power.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a utility application that claims priority toco-pending U.S. Provisional Patent Application entitled, “CellularBaseband Processing”, having Ser. No. 61/618,049, filed Mar. 30, 2012,which is entirely incorporated herein by reference.

BACKGROUND

In radio communication, such as those facilitated by cellular networks,channel characteristics of a signal received by a receiver may vary withtime. Lock target selectors are commonly used in such communicationsystems to select a target that a delay lock loop (DLL) is configured totrack. With these varying channel conditions, a DLL may attempt to lockto a channel tap to facilitate receiving data from a transmitterassociated with, for example, a base station.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood withreference to the following drawings. The components in the drawings arenot necessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the disclosure. Moreover, in thedrawings, like reference numerals designate corresponding partsthroughout the several views.

FIG. 1 is a drawing of an example of processing circuitry forimplementing at least a portion of a wireless communication system, inaccordance with various embodiments of the present disclosure.

FIG. 2 is a diagram of an example of a plurality of channel tapsimplemented in the processing circuitry of FIG. 1, in accordance withvarious embodiments.

FIG. 3 is a diagram of an example of a plurality of channel tapsimplemented in the processing circuitry of FIG. 1, in accordance withvarious embodiments.

FIG. 4 is a flowchart illustrating examples of functionality implementedas portions of logic in the processing circuitry of FIG. 1 according tovarious embodiments of the present disclosure.

FIG. 5 is a flowchart illustrating examples of functionality implementedas portions of logic in the processing circuitry of FIG. 1 according tovarious embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to systems and methods for determiningwhether to lock to a channel tap in a receiving device of a wirelesscommunication system. In a wireless communication system, signals aretransmitted from a transmission station and received via an antenna at areceiving device. A signal received in the wireless communication systemmay be, for example, a multipath signal. A multipath signal may be awireless signal that reaches an antenna using a plurality of paths. Forexample, a wireless signal may be subjected to reflection, refraction,or any other physical interference that causes a wireless signal topropagate through multiple paths.

A receiving device may use a receiving antenna to receive a multipathsignal. Furthermore, the receiving device may employ a set of channeltaps to receive a multipath signal. Channel taps may be configured tolock to portions of the received multipath signal. In variousembodiments of the present disclosure, determining whether to lock to amultipath signal by a particular channel tap may be made based onconsidering a channel tap power as well as a noise power associated withthe received multipath signal. Furthermore, when determining whether tolock to a particular signal, a variable threshold may be used.

Reference is made to FIG. 1 which illustrates an example of processingcircuitry for implementing at least a portion of a wirelesscommunication system, in accordance with various embodiments of thepresent disclosure. Specifically, the non-limiting example of FIG. 1depicts a wireless communication system 102. The wireless communicationsystem 102 includes an antenna 104, a radio frequency (RF) front-endunit 106, processing circuitry 111, and other components forfacilitating receiving signals over the wireless communication system102.

The RF front-end unit 106 includes circuitry for receiving data via theantenna 104. The RF front-end 106 performs operations such as filtering,strengthening of signals, and conversion of signals where conversion mayinclude such operations as analog-to-digital conversion,down-conversion, and so forth. Information is modulated in the receivedsignal, and the same information in a given transmission may becommunicated over different channels due to different paths by eachrespective signal. To this end, a wireless multipath signal may bereceived by the antenna 104 and converted into the digital domain forprocessing a digitally formatted multipath signal 108.

The multipath signal 108 of the RF front-end unit 106 is forwarded tothe processing circuitry 111. In various embodiments, the processingcircuitry 111 is implemented as at least a portion of a microprocessor.The processing circuitry 111 may be implemented using one or morecircuits, one or more microprocessors, application specific integratedcircuits, dedicated hardware, digital signal processors, microcomputers,central processing units, field programmable gate arrays, programmablelogic devices, state machines, or any combination thereof. In yet otherembodiments, the processing circuitry 111 may include one or moresoftware modules executable within one or more processing circuits. Theprocessing circuitry 111 may further include memory configured to storeinstructions and/or code that causes the processing circuitry 111 toexecute data communication functions.

In various embodiments, the processing circuitry 111 may be a clusterpath processor for supporting channel estimation processes. Theprocessing 111 circuitry may be configured to conform to any number ofwireless communication protocols such as, for example, Wideband CodeDivision Multiple Access (WCDMA), High-Speed Data Packet Access (HSDPA),etc. The processing circuitry 111 may be configured to implementmultipath tracking/management using a delay locked loop (DLL), channelestimation, timing generation, timing alignment for downlink transmitdiversity, multipath received signal strength indicator (RSSI)measurements, lock detection, or any combination thereof.

The processing circuitry 111 may comprise a plurality of channel taps116. The plurality of channel taps 116 may be configured to receive themultipath signal. Each channel tap 116 may be associated with lockcircuitry 121 for determining whether to configure a correspondingchannel tap 116 to lock to at least a portion of the received multipathsignal 108. By locking to portions of the multipath signal 108, theprocessing circuitry 111 facilitates receiving information transmittedwirelessly over the wireless communication system 102.

In various embodiments of the present disclosure, lock circuitry 121comprises a plurality of components for determining whether to set thecorresponding channel tap 116 to a lock status or to an unlock status.Lock circuitry 121 may comprise a descrambler/despreader 132, a channelestimation filter 135, a power estimation block 139, an RSSI filter 142,a noise power estimator 145, a lock detector 148, and other components.

A descrambler/despreader 132 may be configured to descramble anddespread signals associated with a corresponding channel tap 116. Inperforming the descrambling and despreading operations, each chip of thesignal is descrambled and despread such that descrambled/despread chipsare accumulated over the spreading interval. The despreader operationmay produce channel symbols from signals associated with thecorresponding channel tap 116 by descrambling and then despreading thesignal using channel spreading sequences and one or more scramblingcodes.

The channel estimation filter 135 generates the instant channelestimation for each tap. The filter is designed based on channelconditions such as, for example, a degree of Doppler effect,interference, a signal-to-noise power ratio, any other channelcharacteristic, or any combination thereof. In various embodiments, thechannel estimation filter 135 comprises a low pass filter. In someembodiments, the channel estimation filter 135 may comprise asingle-pole filter that conforms to the following equation:

y _(n) =α·x _(n)+(1+α)·y _(n−1)

With reference to the equation above, y_(n) represents the output of thechannel estimation filter 135, x_(n) represents the input to the channelestimation filter 135, α represents a predetermined constant associatedwith the channel estimation filter 135, and y_(n) represents theprevious output of the channel estimation filter 135. The output of thechannel estimation filter 135 may comprise one or more complexcomponents such as, for example, an in phase (I) component and aquadrature phase (Q) component.

The power estimation block 139 may be configured to generate a powerestimation based on the output of the channel estimation filter 135. Invarious embodiments, a power estimation block 139 operates on a complexsample associated with the output of the channel estimation filter 135.For example, the power estimation block 139 may generate a signal powerestimation that is modeled as I²+Q².

RSSI filter 142 may receive the output of the power estimation block 139for generating an RSSI signal associated with a corresponding channeltap 116. The RSSI signal may comprise a value that indicates a powermeasurement associated with the corresponding channel tap 116. The RSSIfilter may comprise a low pass filter. In some embodiments, the RSSIfilter 142 may conform to the following equation:

y _(n) =β·x _(n)+(1+β)·y _(n−1)

With reference to the equation above, y_(n) represents the output of theRSSI filter 142, x_(n) represents the input to the RSSI filter 142, βrepresents a predetermined constant associated with the RSSI filter 142,and y_(n) represents the previous output of the RSSI filter 142. To thisend, each channel tap 116 may be associated with a corresponding RSSIsignal, where the corresponding RSSI signal expresses an estimated powerof the corresponding channel tap 116.

According to various embodiments, the RSSI filter 142 is configured toround its output according to a predetermined number of digits. Ratherthan truncating an output that is expressed as an irrational number,which may result in a direct current bias, rounding an output may resultin more optimal processing. Furthermore, coefficients associated withthe RSSI filter 142 may also be rounded to a predetermined number ofdigits.

The lock circuitry 121 may further comprise a noise power estimator 145.The noise power estimator 145 may be configured to generate an estimatednoise power associated with a corresponding channel tap 116. In variousembodiments, the noise power estimator provides a per channel tap noisepower estimation based on the output of the correspondingdescrambler/despreader 132. For example, the noise power estimator 145may generate a noise power estimation by subtracting a pair ofconsecutive output symbols from the output of the descrambler/despreader132 for calculating the noise power. Furthermore, the noise powerestimator 145 may then accumulate one or more chip symbols.

The noise power estimator 145 may be further configured to adjust theoutput of the RSSI filter 142 based on the noise power estimation. Forexample, the noise power estimator 145 may scale or otherwise normalizethe RSSI signal based on the noise power estimation for thecorresponding channel tap 116 or set of channel taps 116.

The lock circuitry 121 may comprise a lock detector 148 for determiningwhether to set a corresponding channel tap 116 to a lock status or to anunlock status. In various embodiments, the lock detector 148 comparesthe output of the RSSI filter 142 to a predetermined threshold range.Moreover, the output of the RSSI filter 142 may be scaled according to anoise power estimation associated to a corresponding channel tap 116.

The lock circuitry 121 may comprise a preset threshold range fordetermining whether to set a particular channel tap 116 to a lock orunlock status. In various embodiments, the preset threshold range may beadjusted or otherwise replaced by a variable threshold 151. The variablethreshold 151 may be determined based on an RSSI value generated fromthe RSSI filter 142, as is discussed in further detail below.

Next, a general description of the operation of the various componentsof the wireless communication system 102 is provided. The processingcircuitry 111 receives a multipath signal 108, where a set of channeltaps 116 are configured to process portions of the multipath signal 108.Each channel tap 116 may lock to the multipath signal 108 depending onchannel characteristics associated with the channel tap 116. Indetermining whether to lock the multipath signal 108, the channel tap116 employs lock circuitry 121. The lock circuitry 121 may be configuredto ultimately set a lock status or an unlock status for a correspondingchannel tap 116.

The lock circuitry 121 generates a one or more symbols associated with achannel tap output using a descrambler/despreader 132. These symbols maybe passed through a channel estimation filter 135 and a power estimationblock 139. Accordingly, an RSSI signal may be generated by an RSSIfilter 142 for determining an RSSI value associated with thecorresponding channel tap 116. RSSI value may reflect a power and/orenergy associated with the corresponding channel tap 116. In variousembodiments, the power and/or energy of a particular channel tap 116 maybe used as a basis for determining whether to configure a particularchannel tap 116 to lock to a multipath signal 108.

Furthermore, a noise power value may be determined for the correspondingchannel tap 116. For example, a noise power estimator 145 may determinea noise power based on one or more symbols of a particular channel tap116. In various embodiments of the present disclosure, the noise powervalue may be used as a basis for determining whether to configure aparticular channel tap 116 to lock to a multipath signal 108. In otherembodiments, a combination of the power/energy of a particular channeltap 116 and the noise power of the particular channel tap 116 is used todetermine whether to set the particular channel tap 116 to a lockstatus.

For example, the RSSI signal, which correlates to the power of aparticular channel tap 116, may be scaled according to the noise powerof the particular channel tap 116. Accordingly, various embodiments ofthe present disclosure are directed to using a per tap metric thatcomprises an RSSI value that is scaled according to the noise power forthe tap.

A lock detector 148 may determine whether to set a corresponding channeltap 116 to a lock status or to an unlock status based on the RSSI valuefor the tap or based on the noise-scaled RSSI value for the tap. Invarious embodiments, a relative or variable threshold range 151 may beused such that the variable threshold range 151 is determined based on aplurality of RSSI values associated with the set of channel taps 116.RSSI values are determined for corresponding channel taps 116 forgenerating a set of RSSI values. A maximum RSSI value may be selectedfrom the set of RSSI values. The variable threshold 151 may be based atleast in part upon the maximum RSSI value. For example, a lock detector148 may be associated with a preset threshold range. This presetthreshold range may be scaled or otherwise modified according to themaximum RSSI value for determining a variable threshold range 151.

In various embodiments, RSSI filter 142 associated with each channel tap116 determines an RSSI value for identifying a maximum RSSI value amongthe plurality of channel taps. The maximum RSSI value and/or variablethreshold range 151 may be stored in a memory included in the processingcircuitry 111. The lock detector 148 may read from the memory forapplying the variable threshold range 151. In other embodiments, thevariable threshold range 151 may be determined based on a noise-scaledRSSI value. To this end, the maximum noise-scaled RSSI value across aset of channel taps 116 may be used to adjust the variable thresholdrange.

Moving on to FIG. 2, shown is an example of a plurality of channel taps116 implemented in the processing circuitry 111 of FIG. 1, in accordancewith various embodiments. The non-limiting example of FIG. 2 illustrateschannel characteristics associated with a set of channel taps 116. Basedon various channel characteristics, the processing circuitry 111 maydetermine whether to configure a particular channel tap 116 to lock to amultipath signal 108 (FIG. 1).

A multipath signal 108 may be received by a set of channel taps 116.Depending on the configuration of each channel tap 116, each channel tap116 receives at least a portion of the multipath signal 108 according toa channel tap signal power 215 and a channel tap noise power 228. Inthis respect, a signal power 215 and a noise power 228 affect the inputinto a particular channel tap 116. As seen in the non-limiting exampleof FIG. 2, a signal power 215 varies across the set of channel taps 116.The noise power 228 may also independently vary across a set of channeltaps 116. Based on at least the signal power 215 and the noise power228, a decision may be made by the processing circuitry 111 whether tolock a particular channel tap 116 to a multipath signal 108.

As seen in the non-limiting example of FIG. 2 channel tap 2 isassociated with the highest channel tap signal power 215 while channeltap 0 is associated with the lowest channel tap signal power 215.Channel tap 0 and channel tap n may correspond to a relatively largenoise power 228. Channel tap 1 may correspond to a relatively mediumnoise power 228 while channel tap 2 may correspond to a relatively lownoise power 228.

The signal power 215 associated with each channel tap 116 may correlateto a corresponding RSSI value. In this respect, the RSSI measurementcomprises an estimation for a channel tap signal power/energy 215. Invarious embodiments of the present disclosure, an RSSI value isdetermined for each channel tap 116 by an RSSI filter 142 (FIG. 1) thatis implemented as a portion of the processing circuitry 111. To thisend, a set of RSSI values are determined for a set of channel taps 116for a particular period of time. The processing circuitry 111 isconfigured to identify or select the maximum RSSI value 234 associatedwith the set of channel taps 116. The maximum RSSI value 234approximates the largest channel tap power 215 associated with the setof channel taps 116.

In various embodiments of the present disclosure, the maximum RSSI value234 is used to adjust a variable threshold range 151 (FIG. 1) used by alock detector 148 (FIG. 1), as is discussed in further detail withrespect to at least FIG. 3.

Turning to FIG. 3, shown is an example of a plurality of channel taps116 implemented in the processing circuitry 111 of FIG. 1, in accordancewith various embodiments. The non-limiting example of FIG. 3 illustratesthe use of RSSI signals/values associated with the set of channel taps116 to adjust a variable threshold 151. FIG. 3 alternatively provides anon-limiting example of using a noise-scaled RSSI value for adjustingthe variable threshold 151. Furthermore, the non-limiting example ofFIG. 3 depicts determining whether to set a channel tap 116 to a lockstatus or unlock status based on a variable threshold range 151 used bya lock detector 148 (FIG. 1).

For each channel tap 116, an RSSI signal that expresses a signal power215 (FIG. 2) for the channel tap 116 may be determined. Furthermore, anoise power 228 (FIG. 2) may be estimated for each channel tap 116.Based at least upon an RSSI signal and a noise power, a noise-scaledRSSI signal may be determined for each channel tap 116. For example, anRSSI signal for a particular channel tap 116 may be scaled according tothe corresponding noise power estimation for the particular channel tap116. Thus, in some embodiments, a noise-scaled RSSI signal is generatedby the processing circuitry 111. In alternative embodiments, anon-scaled RSSI is generated by the processing circuitry 111.

The non-limiting example of FIG. 3 depicts a set of channel taps 116where each channel tap 116 corresponds to a per tap metric 306. Invarious embodiments, the per tap metric 306 comprises an estimated RSSIvalue (e.g., non-scaled RSSI value) for the corresponding channel tap116. In alternative embodiments, the per tap metric 306 comprises anoise-scaled RSSI value for the corresponding channel tap 116. Forexample, channel tap 2 is associated with the largest per tap metric306. A large per tap metric 306 indicates that channel tap 2 isassociated with a relatively large signal power 215, a relatively smallnoise power 228, or any combination thereof. Furthermore, as seen in thenon-limiting example of FIG. 3, channel tap n has a relatively small pertap metric 306 based on the fact that channel tap n is associated with arelatively high noise power 228 and/or tap n is associated with arelative low signal power 215.

The non-limiting example of FIG. 3 further illustrates variousembodiments of the present disclosure directed to adjusting a variablethreshold range 151. The processing circuitry 111 may be associated witha preset upper threshold and a preset lower threshold for determining apreset threshold range. According to various embodiments, the presetupper threshold may be scaled according to the maximum RSSI value 234(FIG. 2) for determining a relative upper threshold 312. For example,the relative upper threshold 312 may be determined by multiplying themaximum RSSI value 234 with a predetermined multiplier or by offsettingthe maximum RSSI value 234 by a predetermined value. To this end, therelative upper threshold 312 may be set to the maximum RSSI value 234minus an offset value. Similarly, the preset lower threshold may also bescaled according to the maximum RSSI value 234 for determining arelative lower threshold 315. Various embodiments are not limited tousing the maximum RSSI value 234 for determining a relative upperthreshold 312 and relative lower threshold 315. For example, a maximumnoise-scaled RSSI value may be used. That is to say, the maximum valueamong the set of noise-scaled RSSI values for a corresponding set ofchannel taps 116 may be used to determine a variable threshold 151.

Accordingly, in response to determining a maximum RSSI value 234, athreshold range may be adjusted, updated, or otherwise modified forgenerating a variable threshold 151. In various embodiments, thevariable threshold 151 is adjusted for each time the maximum RSSI value234 is calculated or a maximum noise-scaled RSSI value is calculated.For example, the maximum RSSI value 234 may be calculated on a per slotbasis or calculated after accumulating a predetermined number ofchips/symbols associated with a channel tap 116.

Furthermore, the non-limiting example of FIG. 3 depicts a portion of theoperation of a lock detector 148 that is configured to be executed inthe processing circuitry 111. The lock detector 148 is configured toset/maintain a lock status or unlock status for a corresponding channeltap 116. For example, the lock detector 148 compares the per tap metric306 for each channel tap 116 to a predetermined threshold range, suchas, for example, the variable threshold range 151.

If, the per tap metric 306 of a particular channel tap 116 falls belowthe variable threshold range 151, then the lock detector 148 sets thestatus of the channel top 116 to unlock. If the per tap metric 306 of aparticular channel tap 116 falls above the variable threshold range 151,then the lock detector 148 sets the status of the channel top 116 tolock. If the per tap metric 306 of a particular channel tap 116 fallswithin the variable threshold range 151, then the lock detector 148holds the previous lock status. For example, if the status of thechannel tap 116 was previously set to unlock, then the lock detector 148maintains the unlock status of the channel tap 116.

As seen in the non-limiting example of FIG. 3, channel tap 0 and channeltap n are both associated with per tap metrics 306 that fall below therelative lower threshold 315 such that the per tap metrics are below thevariable threshold amount 151. Accordingly, the lock detector 148responds by setting channel taps 0 and n to an unlock status. Channeltap 2 is associated with per tap metric 306 that exceeds a relativeupper threshold 312 such that the per tap metric 306 is above thevariable threshold amount 151. Accordingly, the lock detector 148responds by setting channel taps 2 to a lock status. Channel tap 1 isassociated with per tap metric 306 that is within the variable thresholdamount 151. Accordingly, the lock detector 148 holds the current statusof channel tap 1. Thus, the status does not change and channel 1continues to either be set to lock or unlock, depending on the previousstatus.

Referring next to FIG. 4, is a flowchart illustrating examples offunctionality implemented as portions of logic in the processingcircuitry 111 of FIG. 1 according to various embodiments of the presentdisclosure. It is understood that the flowchart of FIG. 4 providesmerely an example of the many different types of functional arrangementsthat may be employed to implement the operation of the processingcircuitry 111 as described herein. As an alternative, the flowchart ofFIG. 4 may be viewed as depicting an example of steps of a methodimplemented in the processing circuitry 111 according to one or moreembodiments. Specifically, the flowchart of FIG. 4 provides anon-limiting example of determining whether to set a particular channeltap status to lock or to unlock with respect to a multipath signal 108(FIG. 1).

To begin, at reference number 403, the processing circuitry 111generates symbols for each channel tap 116 (FIG. 1). The processingcircuitry 111 may implement a descrambler/despreader 132 (FIG. 1) foreach channel tap 116. At reference number 406, the processing circuitry111 performs a channel estimation filter process based on symbolscorresponding to each channel tap 116. The processing circuitry 111 mayimplement a channel estimation filter 135 (FIG. 1) for generating achannel estimation filtered signal based on the symbols for each channeltap 116.

At reference number 409, the processing circuitry 111 generates a signalpower estimation for each channel tap 116. For example, the processingcircuitry 111 may implement a power estimation block 139 (FIG. 1) forgenerating each power estimation value. At reference number 412, theprocessing circuitry 111 performs an RSSI filter operation. Theprocessing circuitry 111 may implement an RSSI filter 142 (FIG. 1) forgenerating an RSSI value corresponding to each channel tap. The RSSIvalue may correlate to a signal power/signal energy 215 (FIG. 2)associated with a corresponding channel tap 116 for a particular pointin time.

In various embodiments, the processing circuitry 111 may generate anRSSI value/signal on a per slot basis. In this respect, the multipathsignal 108 may be transmitted according to a wireless protocol thatdivides wireless signals into transmission intervals such as, forexample, timeslots, frames, blocks, or any other signal division unit.Accordingly, the processing circuitry 111 may be configured to generateRSSI values/signals periodically based on a transmission interval.

At reference number 415, the processing circuitry 111 determines a noisepower estimation for each channel tap 116. For example, the processingcircuitry 111 may implement a noise power estimator 145 (FIG. 1) forestimating a noise power 228 (FIG. 2) associated with each channel tap116.

At reference number 418, the processing circuitry 111 scales orotherwise normalizes the RSSI value/signal for each channel tap 116based on a corresponding noise power estimation. In various embodiments,the processing circuitry 111 scales/normalizes the RSSI value for aparticular channel tap 116 based on the corresponding noise powerestimation for the particular channel tap 116 and the total noise powerfor the set of channel taps 116. Thus, by scaling the RSSI value/signalfor each channel tap 116, the processing circuitry 111 generates a pertap metric 306 (FIG. 3) comprising a corresponding scaled RSSIvalue/signal. Thus, reference number 418 demonstrates embodiments of thepresent disclosure directed to using a noise-scaled RSSI value for eachchannel tap 116.

In alternative embodiments, the RSSI value for each channel tap 116 isnot scaled according to a noise power. In such embodiments, referencenumber 418 may be bypassed. In such a case, the per tap metric 306comprises the RSSI value that is not scaled according to a per tap noisepower.

At reference number 421, the processing circuitry 111 determines whetherthe per tap metric 306 exceeds a relative upper threshold 312 (FIG. 3).For example, the processing circuitry 111 may implement a lock detector148 for each channel tap 116. The lock detector 148 (FIG. 1) may beconfigured to determine whether a per tap metric 306 exceeds a relativethreshold range. If the per tap metric 306 exceeds the relativethreshold range, then the processing circuitry 111 branches to referencenumber 424.

At reference number 424, the processing circuitry 111 sets a particularchannel tap 116 to a lock status. If the scaled per tap metric 306 fallsbelow the predetermined threshold range such that it falls below therelative upper threshold 312, the processing circuitry 111 branches toreference number 425. At reference number 425, the processing circuitry111 determines whether the per tap metric 306 falls below a relativelower threshold 315 (FIG. 3). For example, the processing circuitry 111may implement a lock detector 148 for each channel tap 116. The lockdetector 148 may be configured to determine whether a per tap metric 306falls below a relative threshold range. If the per tap metric 306 doesnot fall below the relative threshold range, then the processingcircuitry 111 terminates and the lock/unlock status for the channel tap116 holds or otherwise remains in the previous state. However, if theper tap metric 306 falls below the relative threshold range, then theprocessing circuitry 111 branches to reference number 427.

At reference number 427, the processing circuitry 111 sets a particularchannel tap 116 to and unlock status. In various embodiments, the statusof each channel tap 116 may be updated on a periodic basis such as, forexample, on a per slot basis.

Referring next to FIG. 5, is a flowchart illustrating examples offunctionality implemented as portions of logic in the processingcircuitry 111 of FIG. 1 according to various embodiments of the presentdisclosure. It is understood that the flowchart of FIG. 5 providesmerely an example of the many different types of functional arrangementsthat may be employed to implement the operation of the processingcircuitry 111 as described herein. As an alternative, the flowchart ofFIG. 5 may be viewed as depicting an example of steps of a methodimplemented in the processing circuitry 111 according to one or moreembodiments. Specifically, the flowchart of FIG. 5 provides anon-limiting example of determining how to adjust a variable thresholdrange 151 (FIG. 1).

At reference number 505, the processing circuitry determines an RSSIvalue/signal for each channel tap 116 (FIG. 1) among a plurality ofchannel taps 116. For example, the processing circuitry 111 mayimplement an RSSI filter 142 (FIG. 1) for each channel tap 116. Atreference number 508, the processing circuitry 111 identifies themaximum RSSI value 234 (FIG. 2) among the set of determined RSSI values.The processing circuitry 111, for example, may employ a rank or sortalgorithm for selecting the largest value among the set of values.

At reference number 511, the processing circuitry 111 scales an upperbound preset threshold value. For example, the processing circuitry 111may comprise preset threshold values that are constant. The processingcircuitry 111 may multiply the preset threshold value with the maximumRSSI value 234 to determine a variable or relative upper threshold 312(FIG. 3). Alternatively, the relative upper threshold 312 may bedetermined by subtracting an offset amount from the maximum RSSI value234.

At reference number 514, the processing circuitry 111 scales a lowerbound preset threshold value. The processing circuitry 111 may multiplythe lower bound preset threshold value with the maximum RSSI value 234to determine a variable or relative lower threshold 315 (FIG. 3).Alternatively, the relative upper threshold 312 may be determined bysubtracting an offset amount from the maximum RSSI value 234.

Accordingly, processing circuitry 111 may store the variable/relativeupper threshold 312 and the variable/relative lower threshold 315 as avariable threshold range 151. A lock detector 148 (FIG. 1) may read thevariable threshold range 151 from the memory of the processing circuitry111. To this end, the lock detector 148 uses a variable threshold range151 to determine whether to set the status of a particular channel tap116 to lock or unlock.

Although the flowchart of FIG. 5 uses a maximum RSSI value 234 fordetermining a relative upper threshold 312 and relative lower threshold315, various embodiments of the present disclosure are not so limited.For example, a maximum noise-scaled RSSI value may be used. That is tosay, the maximum value among the set of noise-scaled RSSI values for acorresponding set of channel taps 116 may be used to determine avariable threshold 151.

The flowcharts of FIGS. 4 and 5 show the functionality and operation ofan implementation of portions of processing circuitry 111. If embodiedin software, each item may represent a module, segment, or portion ofcode that comprises program instructions to implement the specifiedlogical function(s). The program instructions may be embodied in theform of source code that comprises human-readable statements written ina programming language or machine code that comprises numericalinstructions recognizable by a suitable execution system such as theprocessing circuitry 111. The machine code may be converted from thesource code, etc. If embodied in hardware, each item may represent acircuit or a number of interconnected circuits to implement thespecified logical function(s).

Although the flowcharts of FIGS. 4 and 5 show a specific order ofexecution, it is understood that the order of execution may differ fromthat which is depicted. For example, the order of execution of two ormore blocks may be scrambled relative to the order shown. Also, two ormore blocks shown in succession in FIGS. 4 and 5 may be executedconcurrently or with partial concurrence. Further, in some embodiments,one or more of the items shown in FIGS. 4 and 5 may be skipped oromitted. In addition, any number of counters, state variables, warningsemaphores, or messages might be added to the logical flow describedherein, for purposes of enhanced utility, accounting, performancemeasurement, or providing troubleshooting aids, etc. It is understoodthat all such variations are within the scope of the present disclosure.

Also, any logic or application described herein that comprises softwareor code, for example, the processing circuitry 111 (FIG. 1), can beembodied in any non-transitory computer-readable medium for use by or inconnection with an instruction execution system such as, for example, aprocessing circuitry 111 in a computer system or other system. In thissense, the logic may comprise, for example, statements includinginstructions and declarations that can be fetched from thecomputer-readable medium and executed by the instruction executionsystem. In the context of the present disclosure, a “computer-readablemedium” can be any medium that can contain, store, or maintain the logicor application described herein for use by or in connection with theinstruction execution system.

The computer-readable medium can comprise any one of many physical mediasuch as, for example, magnetic, optical, or semiconductor media. Morespecific examples of a suitable computer-readable medium would include,but are not limited to, magnetic tapes, magnetic floppy diskettes,magnetic hard drives, memory cards, solid-state drives, USB flashdrives, or optical discs. Also, the computer-readable medium may be arandom access memory (RAM) including, for example, static random accessmemory (SRAM) and dynamic random access memory (DRAM), or magneticrandom access memory (MRAM). In addition, the computer-readable mediummay be a read-only memory (ROM), a programmable read-only memory (PROM),an erasable programmable read-only memory (EPROM), an electricallyerasable programmable read-only memory (EEPROM), or other type of memorydevice.

It should be emphasized that the above-described embodiments of thepresent disclosure are merely possible examples of implementations setforth for a clear understanding of the principles of the disclosure.Many variations and modifications may be made to the above-describedembodiment(s) without departing substantially from the spirit andprinciples of the disclosure. All such modifications and variations areintended to be included herein within the scope of this disclosure andprotected by the following claims.

Therefore, at least the following is claimed:
 1. A method for aprocessing circuit comprising: generating a set of symbols for a channeltap among a plurality of channel taps based at least upon a multipathsignal; generating a signal power estimation based at least upon afiltering of the set of symbols by a channel estimation filter;generating a received signal strength indication (RSSI) signal based atleast upon the signal power estimation; determining a noise powerestimation for the channel tap based at least upon a portion of the setof symbols; and scaling the RSSI signal based at least upon the noisepower estimation to generate a scaled RSSI signal.
 2. The method ofclaim 1, further comprising setting the channel tap to a lock statusbased at least upon the scaled RSSI signal and a predetermined thresholdrange.
 3. The method of claim 2, wherein the predetermine thresholdrange is variable.
 4. The method of claim 3, wherein the predeterminethreshold range is adjusted according to a maximum RSSI signal among theplurality of channel taps.
 5. The method of claim 3, wherein thepredetermine threshold range is adjusted according to a maximum scaledRSSI signal among the plurality of channel taps.
 6. The method of claim1, wherein determining the noise power estimation comprises subtractinga pair of consecutive symbols of the set of symbols.
 7. A system forsignal processing, comprising: a channel tap configured to obtain atleast a portion of a multi-channel signal for generating a correspondingtap output; a received signal strength indication (RSSI) filterconfigured to generate an RSSI signal based at least upon a signal powerestimation of the tap output; and a lock detector configured to set thechannel tap to a lock status based at least upon the RSSI signal and apredetermined threshold amount.
 8. The system of claim 7, furthercomprising a channel estimation filter configured to generate a channelestimation signal based at least upon the tap output.
 9. The system ofclaim 8, wherein the channel estimation filter comprises a one-poleinfinite impulse response filter.
 10. The system of claim 8, furthercomprising a power estimator configured to generate the signal powerestimation based at least upon the channel estimation signal.
 11. Thesystem of claim 7, wherein the channel tap is one of a plurality ofchannel taps.
 12. The system of claim 11, wherein the predeterminedthreshold amount is configured to be adjusted according to respectivesignal powers corresponding to each of the plurality of channel taps.13. The system of claim 11, wherein the predetermined threshold amountcomprises an upper threshold and a lower threshold, wherein the upperthreshold and lower threshold are configured to be adjusted.
 14. Thesystem of claim 13, wherein the upper threshold and lower threshold areconfigured to be adjusted according to a maximum RSSI signal, themaximum RSSI signal being determined among the plurality of channeltaps.
 15. The system of claim 7, wherein the RSSI filter is furtherconfigured to round a value expressed in the RSSI signal according to apredetermined number of digits.
 16. A system comprising: processingcircuitry configured to: determine received signal strength indication(RSSI) value for each of the plurality of channel taps; identify amaximum RSSI value among the RSSI values; and adjust a variablethreshold range according to the maximum RSSI value.
 17. The system ofclaim 16, wherein the processing circuitry is further configured tomodify a lock status associated with a channel tap in response to thecorresponding RSSI value of the channel tap being outside the variablethreshold range.
 18. The system of claim 16, wherein the processingcircuitry is further configured to hold a lock status associated with achannel tap in response to the corresponding RSSI value of the channeltap being within the variable threshold range.
 19. The system of claim16, wherein the processing circuitry is further configured to determinea respective noise power value for each of the plurality of channeltaps.
 20. The system of claim 19, wherein the processor is furtherconfigured to scale the RSSI filter signal on a per-slot basis.